The present invention pertains in general to fabrication of semiconductor devices and, in particular, to methods for manufacturing high density integrated circuits in which anisotropically etched moats around devices on the integrated circuit are filled with metal to restore surface planarity.
The continued evolution of methods of manufacturing high density integrated circuits has resulted in several alternatives to the junction isolated integrated circuit which has dominated the integrated circuit industry for so many years. The junction isolation approach has basic limitations which affect how closely integrated circuit devices may be spaced with respect to each other in the design of an integrated circuit chip. The spacing between devices must allow for side diffusion since the isolation diffusion region widens with the subsequent diffusions used to form the junctions of the finished semiconductor device. Also since the isolation region and the base regions of the finished integrated circuit are formed using independent photoresist and masking operations, the integrated circuit layout in a junction isolated approach must allow for alignment tolerances. Further, the spacing of semiconductor device regions must allow for the voltage depletion between regions during normal operation. These requirements derive from the fact that since the isolating junction is a potentially active device region, it must not touch or reach through to the base region of an associated integrated circuit device if correct electrical operation is to be maintained.
Several passive isolation schemes have been proposed to eliminate the difficulties associated with junction isolation in integrated circuit fabrication. One method substitutes an oxidation for the deep isolation diffusion such that by converting exposed silicon at the surface into an oxide, an insulating region is formed between adjacent semiconductor devices. A basic advantage to this approach is that it eliminates the base alignment sensitivity associated with a junction isolated approach. If the base region should touch the isolation, it is merely touching a passive oxide area and there is no electrical effect on the integrated circuit.
In spite of its advantages, the process of oxidizing from the upper surface to form a passive isolation region suffers from inherent limitations associated with the oxide growth process. The conversion of exposed silicon to oxide to a given depth below an exposed silicon surface requires the growth of approximately twice that amount of oxide above the surface. For thicknesses beyond 20,000 angstroms of oxide, oxide growth slows to the point of impracticality and thus the oxide isolation approach is limited to semiconductor devices formed in epitaxial layers from one and a half microns to 2 microns thick. Thus the approach requires critically thin epitaxial layers which are more difficult and more costly to provide and which place limitations on the kinds of electrical performance attainable from the resulting semiconductor devices on the final integrated circuit.
Another method proposed for overcoming the difficulties associated with junction isolation is the use of anisotropic etching to form a moat or V-groove which physically isolates a semiconductor device region. Diffused isolation processes and oxide isolation processes are basically isotropic, i.e., the formation of the isolation region proceeds at the same rate in all directions. In contrast, the fundamental nature of anisotropic etchants is to etch along a particular plane of the crystal lattice more rapidly than along other planes of the crystal lattice. A typical anisotropic etchant attacks the [111] plane of the crystal lattice approximately 25 times faster than it attacks the [100] plane of that same lattice. Thus in an integrated circuit structure comprising a [100] crystal substrate upon which has been formed an overlying epitaxial layer which will consequently also have a [100] crystal orientation, anisotropic etching results in the formation of V-grooves whose sidewalls are slanted at approximately 54.degree. to the semiconductor surface. These steeply sloped V-grooves allow adjacent semiconductor device regions to be closely located with respect to each other even in the case of realtively thick epitaxial layers.
In integrated circuits which take advantage of the reduced device spacing attainable using V-groove isolation techniques, the final integrated circuit density is often limited by the location and spacing of the interconnection metal which must be used to functionally interconnect the devices of the finished integrated circuit. Paradoxically, the high density air-isolated device structure attainable using V-groove isolation introduces new problems in a "metal limited" integrated circuit of this type. This problem arises because the surface irregularities associated with the formation of V-grooves create a variety of photoresist and mask exposure problems which make it impossible to attain the metal spacing tolerances achievable with a planar semiconductor surface.